Silicon Labs /EFR32FG23B010F128GM40 /FRC_S /CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RANDOMTX)RANDOMTX 0 (UARTMODE)UARTMODE 0 (LSBFIRST)BITORDER 0 (FCDMODE0)TXFCDMODE 0 (FCDMODE0)RXFCDMODE 0BITSPERWORD 0RATESELECT 0 (X0)TXPREFETCH 0 (TXFETCHBLOCKING)TXFETCHBLOCKING 0 (X0)SEQHANDSHAKE 0 (PRBSTEST)PRBSTEST 0 (LPMODEDIS)LPMODEDIS 0 (WAITEOFEN)WAITEOFEN 0 (RXABORTIGNOREDIS)RXABORTIGNOREDIS 0 (SKIPTXTRAILDATAWHITEN)SKIPTXTRAILDATAWHITEN 0 (SKIPRXSUPSTATEWHITEN)SKIPRXSUPSTATEWHITEN

SEQHANDSHAKE=X0, TXFCDMODE=FCDMODE0, BITORDER=LSBFIRST, RXFCDMODE=FCDMODE0, TXPREFETCH=X0

Description

No Description

Fields

RANDOMTX

Random TX Mode

UARTMODE

Data Uart Mode

BITORDER

Data Bit Order.

0 (LSBFIRST): Least Significant bit in each word is sent/received first.

1 (MSBFIRST): Most Significant bit in each word is sent/received first.

TXFCDMODE

TX Frame Control Descriptor Mode

0 (FCDMODE0): FCD0 is reloaded when SCNT reaches 0

1 (FCDMODE1): Use FCD0 for the first sub-frame, then switching between FCD0 and FCD1 for following sub-frames

2 (FCDMODE2): Use FCD0 for the first sub-frame, then FCD1 is used for all following sub-frames

3 (FCDMODE3): Use alternating FCD0 / FCD1 for each complete frame

RXFCDMODE

RX Frame Control Descriptor Mode

0 (FCDMODE0): FCD2 is reloaded when SCNT reaches 0

1 (FCDMODE1): Use FCD2 for the first sub-frame, then switching between FCD2 and FCD3 for following sub-frames

2 (FCDMODE2): Use FCD2 for the first sub-frame, then FCD3 is used for all following sub-frames

3 (FCDMODE3): Use alternating FCD2 / FCD3 for each complete frame

BITSPERWORD

Bits Per Word, for first word in a frame

RATESELECT

MODEM rate select

TXPREFETCH

Transmit prefetch data

0 (X0): The frame controller will start preparing transmit data when entering the TX state. This setting may be used in most cases.

1 (X1): The frame controller will start preparing transmit data already in the TXWARM, RX2TX or TX2TX state. This setting must be used to avoid transmit underflow in the cases where no preamble or frame synchronization is inserted by the modulator (i.e. typically when the MODEM control fields TXBASES is zero and SYNCDATA is set).

TXFETCHBLOCKING

Transmit fetch data blocking

SEQHANDSHAKE

Sequencer data handshake

0 (X0): The sequencer may read transmit or read data through the FRCRD command, but it will not wait for the sequencer to do so before proceeding to parse transmit or receive data.

1 (X1): The frame controller will require that the sequencer program uses the FRCRD command to read both transmit and receive data which the frame controller stores in the DATABUFFER register. If data is not read with this field set, the overflow (RXOF) or underflow (TXUF) will be set.

PRBSTEST

Pseudo-Random Bit Sequence Testmode

LPMODEDIS

Disable FRC low power

WAITEOFEN

Enable STATE_TX_WAITEOF

RXABORTIGNOREDIS

Disable ignoring CMD_RXABORT

SKIPTXTRAILDATAWHITEN

AoX skip data whitening

SKIPRXSUPSTATEWHITEN

AoX skip data whitening

Links

()